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    Preparation of semiconductor




    The manufacturing process of chip can be divided into many steps, such as sand raw material (quartz), silicon ingot, wafer, photolithography, etching, ion implantation, metal deposition, metal layer, interconnection, wafer testing and cutting, core packaging, level testing, packaging, etc., and each step contains more detailed processes.
    1. Sand: silicon is the second richest element in the earth's crust, and the deoxidized sand (especially quartz) contains at most 25% silicon element, which exists in the form of silicon dioxide (SiO2), which is also the foundation of semiconductor manufacturing industry.


    2. Silicon smelting: 12 inch / 300 mm wafer level, the same below. The silicon that can be used in semiconductor manufacturing quality can be obtained through multi-step purification. The scientific name is electronic grade silicon (EGS). On average, there is only one impurity atom in every one million silicon atoms. This figure shows how to get large crystals through silicon purification smelting, and the final result is silicon ingot.
    3. Single crystal silicon ingot: it is basically cylindrical in shape, with a weight of about 100kg and a silicon purity of 99.9999%.
    4. Ingot cutting: a single wafer is cut horizontally into a circle, which is often called wafer. By the way, do you know why the wafers are round?
    5. Wafer: the cut wafer becomes almost flawless after polishing, and the surface can even be used as a mirror.
    6. Photoresist: the blue part in the picture is the photoresist liquid poured during the wafer rotation, similar to the traditional film. Wafer rotation can make photoresist spread very thin, very flat.
    7. Lithography: the photoresist layer is then exposed to ultraviolet (UV) through the mask and becomes soluble. The chemical reaction during this period is similar to the change of film at the moment when the mechanical camera shutter is pressed. The mask is printed with a pre-designed circuit pattern, through which ultraviolet light shines on the photoresist layer, each layer of the microprocessor circuit pattern will be formed.
    8. Dissolving photoresist: the photoresist exposed to ultraviolet light is dissolved during the photolithography process, and the pattern left after removal is consistent with that on the mask.
    9. Etching: use chemicals to dissolve the exposed wafer parts, while the remaining photoresist protects the parts that should not be etched.
    10. Remove photoresist: after etching, the mission of photoresist is announced to be completed, and the designed circuit pattern can be seen after all the photoresists are removed.
    11. Ion implantation: in a vacuum system, the solid material is irradiated (implanted) with the accelerated ions of the atoms to be doped, so as to form a special implantation layer in the implanted area and change the conductivity of silicon in these areas. After the acceleration of electric field, the speed of implanted ion current can exceed 300000 km / h.
    12. Remove photoresist: after the ion implantation, the photoresist is also removed, and the injection area (green part) has been doped with different atoms. Notice that the green is different from before.
    13. Transistor ready: so far, the transistor has been basically completed. Three holes are etched on the insulating material (magenta) and filled with copper to interconnect with other transistors.
    14. Electroplating: a layer of copper sulfate is electroplated on the wafer, and copper ions are precipitated on the transistor. Copper ions will move from positive (anode) to negative (cathode).
    15. Copper layer: after electroplating, copper ions are deposited on the wafer surface to form a thin copper layer.
    16. Polishing: polish off the surplus copper, that is, polish the wafer surface.
    17. Metal layer: transistor level, a combination of six transistors, about 500 nm. A composite interconnection metal layer is formed between different transistors, and the specific layout depends on the different functions required by the corresponding processor. The surface of the chip looks very smooth, but in fact it may contain 20 layers of complex circuits. After amplification, we can see extremely complex circuit networks, such as the futuristic multi-layer highway system.
    18. Wafer test: core level, about 10 mm / 0.5 inch. This is part of the wafer, which is undergoing the first functional test, using the reference circuit pattern to compare with each chip.
    19. Slicing: wafer level, 300 mm / 12 inch. Cut the wafer into blocks, each of which is the core of the chip (die). The transimpedance amplifier in our to can package is the form of die.
    20. Discard defective core: wafer level. The defective kernel found in the test process is discarded, leaving good preparation for the next step
    21. encapsulation



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